The present invention relates to an improved input amplifier circuit which may be employed in a semiconductor integrated circuit or the like.
In a semiconductor integrated circuit, noise signals are most likely to enter an input amplifier circuit at its input terminal. If such an external noise signal is indiscriminately applied to the input amplifier circuit, the integrated circuit may operate erroneously. In order to overcome this difficulty, an input amplifier circuit based on a Schmitt trigger circuit may be employed.
FIG. 1 is a circuit diagram showing an example of a conventional input amplifier circuit employing a Schmitt trigger circuit configuration implemented with N channel MOS field-effect transistors (FETs). In FIG. 1, reference numeral 1 designates a Schmitt trigger amplifier, 2 an input terminal, 3 an output terminal, 4 a first power source terminal for supplying a voltage V.sub.DD to drive the Schmitt trigger amplifier 1, and 5 a return line for supplying a return line voltage V.sub.SS such as a ground level, the return line being a second power source terminal. An FET 6 is of the depletion type, while FETs 7 and 8 are of the enhancement type. The FETs 7 and 8 are connected at a junction point 9 forming a series circuit. The input terminal 2 is connected to the gates of the FETs 7 and 8. The FETs 6 and 7 are connected at a junction point which is further connected to the gate of the FET 6, to the gate of an enhancement-type FET 10, and to the output terminal 3. The drain and source electrodes of the FET 10 are connected to the power source terminal 4 and the junction point 9, respectively.
The operation of this input amplifier circuit when a signal is applied to the input terminal will be described with respect to the case where the input signal is a positive logic signal.
In the case where a voltage lower than the threshold voltage of the FET 8 is applied to the input terminal 2, the Schmitt trigger amplifier 1 is maintained in a steady state. The FETs 7 and 8 are then non-conductive (off), and, because the FET 6 is a depletion-type MOS transistor, the potential at the output terminal 3 is a high level. As the output terminal 3 is at the high level, the FET 10 is rendered conductive, and thus the potential at the junction point 9 is much higher than that at the input terminal 2.
When the potential at the input terminal 2 exceeds the threshold voltage V.sub.T8 of the FET 8, the FET 8 is rendered conductive, that is, it is in a low impedance state, so that current flows from the source of the feedback FET 10 through the FET 8 via the junction point 9. In this operation, the FET 7 is nonconductive, that is, it is in a high impedance state. When the input voltage increases further and exceeds the sum V.sub.IH of the threshold value V.sub.TH of the FET 7 and the potential V.sub.9 H at the junction point 9, both FETs 7 and 8 become conductive. The potential at the output terminal 3 is then set to the low level, whereby the FET 10 is rendered nonconductive. Even when the input voltage exceeds the above-described value V.sub.IH, this state is maintained. The relation between input voltage and output voltage is thus as indicated by a line a in FIG. 2.
The case where the input voltage decreases from a value larger than the value V.sub.IH will now be considered. When the input voltage becomes lower than the sum V.sub.IL of the threshold voltage V.sub.7L of the FET 7 and the potential V.sub.9L at the junction point 9, the FET 7 is rendered non-conductive. As the FET 6 is a depletion-type MOS transistor, the potential of the output terminal 3 will then be raised to a high level by the FET 6. The potential V.sub.9L at the junction point 9 when the low impedance state of the FET 7 is changed to the high impedance state is lower than the potential V.sub.9H at this same point when the high impedance state of the FET 7 is changed to the low impedance state. Accordingly, the input voltage V.sub.IH in moving from the low impedance state of the FET 7 to the high impedance state is lower than that in the case of changing from the high impedance state of the FET 7 to the low impedance state. The relation between the input voltage and output voltage in this operation is as indicated by the line b in FIG. 2.
The Schmitt trigger amplifier circuit arranged as described above thus has two different threshold voltages: the threshold voltage V.sub.IH in shifting the input voltage from the low level to the high level and the threshold voltage V.sub.IL in shifting the input voltage from the high level to the low level. Accordingly, in the Schmitt amplifier circuit 1 constructed as described above, there is little likelihood of an erroneous operation occurring with a noise input which rises to the high level from the low level and with a noise input which falls to the low level from the high level when compared with an input amplifier circuit having only one threshold value V.sub.N (V.sub.IH &gt;V.sub.N &gt;V.sub.IL). This will be described in more detail with reference to FIG. 3.
FIG. 3 shows an input voltage wavefrom A and an output voltage waveform B derived from the waveform A. If a noise input voltage is higher than V.sub.N (the threshold voltage in an input amplifier circuit having only one threshold voltage) but lower than V.sub.IH, then the output voltage is unchanged. Also, when the input voltage is higher than the threshold value, the output voltage falls to low state, and the noise input voltage is lower than V.sub.IH, the output voltage is maintained unchanged.
In the above-described Schmitt trigger amplifier circuit 1, it is theoretically possible to decrease the probability of erroneous operation by increasing the threshold voltage V.sub.IH and decreasing the threshold voltage V.sub.IL. However, in practice, it is difficult to precisely set these voltages to desired levels because the voltages depend on the electrical characteristics of a signal source circuit (now shown) connected to the input terminal 2. Thus, it is rather difficult to make the Schmitt trigger amplifier circuit 1 eliminate noise signals as desired.